1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor substrate. In particular, the present invention relates to a method for manufacturing a semiconductor substrate in which a single-crystal semiconductor layer is bonded to a substrate having an insulating surface such as glass or the like. Further, the present invention relates to semiconductor devices which have circuits including thin film transistors (hereinafter, referred to as TFTs) that use the semiconductor substrate. For example, the present invention relates to electro-optical devices typified by liquid crystal display panels, or electronic devices which have light-emitting display devices including an organic light-emitting element as a component.
Note that a semiconductor device refers to any device which can function by utilizing semiconductor characteristics in this specification. Electro-optical devices, semiconductor circuits, and electronic devices are all semiconductor devices.
2. Description of the Related Art
In recent years, attention has focused on a technique for making a thin film transistor (TFT) by using a semiconductor thin film (having a thickness of about several to about several hundreds of nanometers) formed over a substrate having an insulating surface. The thin film transistors are widely applied to electronic devices such as ICs and electro-optical devices, and their rapid development as switching elements for image display devices is particularly desired.
A semiconductor substrate called a silicon-on-insulator (SOI substrate) that has a thin single-crystal semiconductor layer on an insulating layer has been developed instead of a silicon wafer that is manufactured by thinly slicing an ingot of a single-crystal semiconductor. The SOI substrates are spreading as substrates in manufacturing microprocessors or the like. This is because an integrated circuit using an SOI substrate attracts attention as an integrated circuit in which parasitic capacitance between a drain of a transistor and a substrate can be reduced, performance of the semiconductor integrated circuit can be improved, and low power consumption is achieved.
As a method for manufacturing SOI substrates, a hydrogen ion implantation separation method is known (e.g., see Patent Document 1: U.S. Pat. No. 6,372,609). The hydrogen ion implantation separation method is a method by which hydrogen ions are implanted into a first silicon wafer whose surface is thermally oxidized to form a microbubble layer at a predetermined depth from the surface, and then, the surface is located in close contact with a second silicon wafer with the thermal oxidized film interposed therebetween, and a thin silicon layer (SOI layer) is bonded to the second silicon wafer using the microbubble layer as a cleavage plane. In addition to heat treatment for separating an SOI layer, it is necessary to perform heat treatment in an oxidizing atmosphere to form an oxide film on the SOI layer, remove the oxide film, and perform heat treatment at 1000° C. to 1300° C. in a reducing atmosphere to increase bonding strength.
On the other hand, attempts have been made to form an SOI layer on an insulating substrate such as glass or the like. As an example of SOI substrates in which SOI layers are formed on glass substrates, an SOI substrate in which a thin single-crystal silicon layer is formed on a glass substrate having a coating film by a hydrogen ion implantation separation method is known (see Patent Document 2: U.S. Pat. No. 7,119,365). In this case also, a thin single-crystal silicon layer (SOI layer) is formed on the glass substrate in such a way that a microbubble layer is formed at a predetermined depth from the surface by implantation of hydrogen ions to a piece of single-crystal silicon, the glass substrate and the piece of single-crystal silicon are bonded to each other, and the piece of single-crystal silicon is separated using the microbubble layer as a cleavage plane.
A glass substrate is rectangular in shape and had a size of 300 mm×400 mm for the first generation in the beginning of 1990, which has grown to 680 mm×880 mm or 730 mm×920 mm for the fourth generation in 2000.
In contrast, size of semiconductor substrates is not so varied because semiconductor substrates are manufactured by forming an ingot of 20 cm to 30 cm in diameter by a Czochralski method (a CZ method), and slicing the ingot with a diamond blade or the like so that the slice has a thickness of about 0.5 mm to about 1.5 mm to make a circle wafer.
Accordingly, in the case of manufacturing an active matrix display device using a glass substrate which is larger than a semiconductor substrate, a plurality of semiconductor substrates is used for a single glass substrate. At that time, there has been a problem in that it is difficult to form a plurality of single-crystal semiconductor layers over the single glass substrate without a space by a hydrogen ion implantation separation method. There is a chamfer portion so as to prevent chipping or cracking at an end face of a semiconductor substrate, and the semiconductor substrate is not located in close contact with the glass substrate at the chamfer portion; therefore, a single-crystal semiconductor layer is not formed over the glass substrate. In addition, there is a portion where ion doping is incapable of being performed or a thin film is incapable of being formed in the end portion of the surface of the semiconductor substrate because the end portion of the semiconductor substrate is held by a jig at the time of ion doping or of film formation. Therefore, the portion is incapable of being separated from the single-crystal semiconductor layer, and the single-crystal semiconductor layer is incapable of being formed over the glass substrate.
Since the chamfer portion or the portion to be held by a jig generally has about several millimeters, there is at least a space of several millimeters between a plurality of single-crystal semiconductor layers. In general, in the case where a 40-inch high-definition television is used, it is necessary to narrow a space to about 200 μm to about 300 μm.